1. Field of the Invention
The present invention generally relates to a non-volatile semiconductor memory device. More particularly, the present invention relates to a non-volatile semiconductor memory device conducting a data write or data erase operation based on a prescribed unit region.
2. Description of the Background Art
A flash memory is a typical example of electrically erasable non-volatile memories.
FIG. 22 is a conceptual diagram showing the memory cell structure of the flash memory.
Referring to FIG. 22, a memory cell MC of the flash memory includes a source 2 and a drain 3. The source 2 and the drain 3 are n+ regions, and are formed at a p-type substrate 1. The memory cell MC further includes a floating gate 4 and a control gate 5. The floating gate 4 and the control gate 5 are deposited on the p-type substrate 1 so as to be insulated by an insulating film 6. In particular, an insulating film between the floating gate 4 and the control gate 5 is also referred to as an inter-poly insulating film 6a, and an insulating film between the floating gate 4 and the p-type substrate 1 is also referred to as a tunnel insulating film 6b. Thus, the memory cell MC corresponds to an n-channel field effect transistor formed on the p-type substrate 1.
The control gate 5 is coupled to a word line WL for selecting the memory cell MC. The source 2 and the drain 3 are respectively coupled to a source line SL and a bit line BL.
In the initial state, i.e., in the data erase state, electrons 7 are drawn out of the floating gate 4 of the memory cell MC.
In contrast, a data write operation to the memory cell MC is conducted by injection of the electrons 7 into the floating gate 4 by Fowler-Nordheim tunneling. The memory cell MC having the electrons 7 injected into the floating gate 4, i.e., in the data write state, has a higher threshold voltage than in the data erase state.
Accordingly, selectively writing the data to a part of the memory cell group in the data erase state enables the storage data to be read according to the threshold voltage value of each memory cell MC. The storage data is read in the following manner: with the bit line being precharged, a fixed voltage is applied to the word line WL connected to the control gate so as to cause memory discharge for a prescribed period, and then a potential on the bit line is detected.
FIGS. 23A to 23C are conceptual diagrams illustrating data erase, write and read operations of the flash memory.
Note that FIGS. 23A to 23C illustrate the respective operations to and from a memory cell group arranged in two rows by two columns. Word lines WL1 and WL2 are provided corresponding to the respective memory cell rows, and bit lines BL1 and BL2 are provided corresponding to the respective memory cell columns. The source line SL is provided in common to the memory cells.
In the specification, a prescribed unit region that is subjected to a single data write operation or data erase operation is referred to as a xe2x80x9csectorxe2x80x9d. A single sector herein corresponds to a memory cell group selected by a single word line.
Referring to FIG. 23A, the data erase operation is conducted on a sector-by-sector basis. The word line WL1 of the selected sector is set to a negative high voltage Vnn, as well as the source line SL and the bit lines BL1, BL2 are grounded. The word line WL2 of the non-selected sector is grounded.
As a result, the negative high voltage Vnn and the ground voltage Vss are respectively applied to the control gates and sources of the memory cells of the selected sector. Thus, in each memory cell of the selected sector, electrons are drawn out of the floating gate by the Fowler-Nordheim tunneling, whereby the data is erased.
Referring to FIG. 23B, the data write operation is conducted on a sector-by-sector basis. The word line WL1 of the selected sector is set to a high voltage Vpp with the source line SL being opened.
According to the write data, a write inhibit voltage Vdi and a ground voltage Vss are selectively applied to each bit line. In a memory cell receiving the high voltage Vpp and the ground voltage Vss at its control gate and drain through the word line and the bit line, respectively, electrons are injected into the floating gate by the Fowler-Nordheim tunneling, whereby the data is written thereto. However, the data is not written to a memory cell receiving the high voltage Vpp and the write inhibit voltage Vdi at its control gate and drain, respectively.
In order to prevent drain disturb, a voltage Vwi having about the same value as that of the write inhibit voltage Vdi is applied to the word line WL2 of the non-selected sector.
Thus, controlling the respective drain voltages of the plurality of memory cells coupled to the same word line WL through the bit lines allows for the selective data write operation.
For example, in FIG. 23B, the word line WL1 is selected to be driven to the high voltage Vpp. In response to this, the data is written to a memory cell MCa coupled to the bit line BL1 of the ground voltage Vss. However, the data is not written to a memory cell MCb coupled to the bit line BL2 of the write inhibit voltage Vdi.
Thus, by first erasing the data from each memory cell MC and then selectively writing the data thereto, only the threshold voltage of the written memory cell is increased.
Referring to FIG. 23C, in the data read operation, each bit line is precharged to a prescribed voltage Vdr. Then, a prescribed data read voltage Vwr is applied to the selected word line for a prescribed period. Thus, the control gates of the corresponding memory cells are set to the prescribed voltage Vwr. The word line WL2 of the non-selected sector is retained at the ground voltage Vss.
By appropriately setting the voltages Vwr, Vdr in view of the threshold voltage of the written memory cell, the charges precharged in the written memory cell are stored therein. However, the charges precharged in the non-written memory cell are discharged therefrom. Accordingly, the data can be read by detecting the amount of charges remaining on the bit line.
Thus, depending on whether the electrons are injected into the floating gate or not, the data can be written to each memory cell MC in a non-volatile manner as well as the storage data thereof can be read.
FIG. 24 is a conceptual diagram showing the threshold voltage distribution of the memory cells of the flash memory.
Referring to FIG. 24, a memory cell in the data write state, i.e., having the storage data level of xe2x80x9c0xe2x80x9d, has a higher threshold voltage than that of a memory cell in the data erase state, i.e., having the storage data level of xe2x80x9c1xe2x80x9d.
In each state, the memory cell group has a variation in threshold voltage distribution. Therefore, in view of this variation, a data read level Vtr is set so that the respective threshold voltages can be distinguished from each other. Thus, the data can be read from the memory cell.
In other words, in the data read operation, prescribed applied voltages to the memory cells, i.e., Vwr and Vdr in FIG. 23C, are set so that a current flows through a transistor whose threshold voltage corresponds to the data read level Vtr.
Recently, so-called multi-level technology capable of writing a plurality of data levels to each memory cell has been used for reduced costs and increased capacity of the flash memory. For example, in a 2 bits/cell flash memory, two-bit information is stored in a single memory cell.
FIG. 25 is a conceptual diagram showing the threshold voltage distribution of the memory cells of the 2 bits/cell flash memory.
Referring to FIG. 25, in the 2 bits/cell flash memory, three data write states L1, L2 and L3 are defined in addition to the data erase state corresponding to the storage data level ofxe2x80x9c11xe2x80x9d. For example, the data write states L1, L2 and L3 respectively correspond to the storage data levels of xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d and xe2x80x9c10xe2x80x9d.
Appropriately setting the data write conditions such as an applied voltage level in the data write operation (the high voltage Vpp in FIG. 23B) makes the threshold voltage distributions of the data write states of the respective data levels different from each other.
Data read levels Vtr1 to Vtr3 are set at the respective boundaries of the threshold voltage distributions of the data write states of the three data levels. Accordingly, a memory cell storing such multi-level data must have tighter threshold voltage distributions. In other words, variation must be suppressed in the data write state of each data level.
The difference in data write characteristics between the memory cells resulting from the manufacturing variation is problematic in terms of suppressing the variation in threshold voltage in each data write state. For example, the variation results from the difference in wiring width of the control gate, i.e., the word line, thickness of the inter-poly insulating film between the control gate and the floating gate, thickness of the tunnel insulating film between the semiconductor substrate and the floating gate, and the like.
For example, a memory cell having a narrower word line and thicker insulating film and tunnel insulating film is less susceptible to electron injection for a data write operation. Therefore, setting the standard data write conditions adapted to the standard data write characteristics would increase the time required for writing.
In contrast, a memory cell having a wider word line and thinner inter-poly insulating film and tunnel insulating film is more susceptible to electron injection, whereby the data is written at a high speed. Accordingly, when the data is written on the standard data write conditions, an increased number of memory cells are slightly over-programmed with the electrons excessively injected therein, resulting in a variation in threshold voltage after the data write operation.
Accordingly, in the flash memory, it is desirable to adjust the data write conditions based on a unit write region that is subjected to a single data write operation, i.e., on a sector-by-sector basis. For example, in the operation testing, optimal data write conditions of every sector are calculated and stored in the memory device. In the normal operation, the optimal data write conditions corresponding to the sector of interest are read upon every write operation, so that the data is written based on the optimal data write conditions.
In general, when the data is written to the flash memory, a data write pulse, i.e., a voltage signal having a prescribed voltage amplitude and pulse width, is applied to the control gate. In other words, the data write conditions are set according to the voltage amplitude and pulse width of the data write pulse.
Japanese Laid-Open Publication No. 10-334073 discloses the technology of pre-storing the write condition information of a flash memory incorporated into a microcomputer, by using a partial region of a memory cell array of the flash memory. When the data is written to a memory cell in a normal region, the pre-stored write condition information is read in order to set the write conditions, i.e., the voltage level and pulse width of the data write pulse, based on the information.
FIG. 26 is a schematic block diagram showing the overall structure of a flash memory of the conventional example having setting of the data write conditions of each sector pre-stored therein.
Referring to FIG. 26, the flash memory 8 of the conventional example includes a memory array 10, a row decoder 20, a column decoder 30, a column selection gate and sense amplifier 35, a data register and data write circuit 40.
The memory array 10 has a plurality of memory cells arranged in a matrix. Each memory cell has the structure shown in FIG. 22.
The memory array 10 has a normal region 12 for normal data storage, and a write condition storage region 14 for storing the data write conditions in writing the data to the normal region 12.
The normal region 12 is divided into a plurality of sectors. In the structure of FIG. 26, a memory cell group of the same row coupled to the same word line WL forms the same sector. In other words, each sector has a plurality of memory cells that are subjected to a single data read operation and a single data write operation.
In the flash memory 8, the data write operations are set on a sector-by-sector basis so as to appropriately conduct the data write operation. The structure of the write condition storage region 14 will be specifically described later.
The row decoder 20 receives a sector address SA, and selects a sector by selective activation of the word line according to the sector address SA.
The column decoder 30 conducts column selection according to a column address CA. In the data read operation, the column selection gate and sense amplifier 35 outputs the read data according to a voltage on the bit line corresponding to the memory cell column selected by the column decoder 30.
The data register and data write circuit 40 stores the write data to the sector of interest, and also sets the respective voltages of the bit lines BL according to the stored write data.
The flash memory 8 further includes a control signal buffer 50, a multiplexer 52, a sector address buffer 54, a command decoder 56, a column address counter 58, a control circuit 60, and a data input buffer 65.
The control signal buffer 50 receives an external control signal for generating an internal control signal and a multiplexer control signal. The multiplexer control signal switches input/output to/from multiplexer 52. For example, at an input of command, the external control signal corresponding to the input command is input to the control signal buffer 50. The multiplexer 52 transmits a signal (i.e. command) from the external input/output (I/O) to the command decoder 56 in response to the multiplexer control signal based on the input external control signal. The control circuit 60 receives the internal control signal to perform predetermined operations, e.g. data read operation, data write operation, and data erase operation corresponding to the output of command decoder 56.
In the data read operation, an address signal is input from the external I/O after a read command. The external control signal corresponding to the read command is input to the control signal buffer 50. The multiplexer 52 transmits the address signal from the external I/O to the sector address buffer 54 in response to the multiplexer control signal based on the input external control signal. The control circuit 60 receives the internal control signal and controls column-related circuits (e.g. the column decoder 30, column selection gate and sense amplifier 35, and data register and data write circuit 40) to perform predetermined read operation with selecting the sector corresponding to the input address signal. Furthermore, an external control signal for outputting read data is input to the control signal buffer 50. The multiplexer 52 transmits the read data from the data output buffer 75 to the external I/O, in response to the multiplexer control signal based on the input external control signal.
In the data write operation, an address signal is input from the external I/O after a write command. The external control signal corresponding to the write command is input to the control signal buffer 50. The multiplexer 52 transmits the address signal from the external I/O to the sector address buffer 54 in response to the multiplexer control signal based on the input external control signal. Next, each write data is set to the data register and data write circuit 40 through column selection gate and sense amplifier 35. At this timing, an external control signal to transmit write data from the external I/O to the data input buffer 65 is input to the control signal buffer 50. The multiplexer 52 transmits the write data to the data input buffer 65 in response to the multiplexer control signal based on the input external control signal. The column address counter 58 conducts a count-up operation to sequentially address a plurality of memory cell columns and transmits a column address CA to the column decoder 30. Write data sequentially input from the external I/O are set to the data register and data write circuit 40 according to the counted-up column addresses.
Next to the write command, a confirm command is input from the external I/O. The external control signal corresponding to the confirm command is input to the control signal buffer 50. The multiplexer 52 transmits a signal (i.e. confirm command) from the external I/O to the command decoder 56 in response to the multiplexer control signal based on the input external control signal. The control circuit 60 starts a data write operation in response to the output of the command decoder 56 and the internal command signal. In the data write operation, a data write pulse is applied to each of the memory cells included in the selected sector by the address signal.
In the data write operation, the control circuit 60 gives an instruction to the row decoder 20 on the application timing of the data write pulse to the word line and the pulse width thereof.
The flash memory 8 further includes a selector 70, a data output buffer 75, a high-voltage generating circuit 80, and a write condition information register 85.
The selector 70 transmits the read data from the column selection gate and sense amplifier 35 to either the data output buffer 75 or the write condition information register 85. The data read from the normal region 12 is transmitted from the selector 70 to the data output buffer 75, and is output as read data to the external I/O through the multiplexer 52. The data read from the write condition storage region 14 is transmitted to the write condition information register 85, and held therein.
The high-voltage generating circuit 80 produces a program voltage Vpgm according to the data retained in the write condition information register 85.
In the data write operation, the row decoder 20 applies a data write pulse to the word line WL corresponding to the sector address SA, based on the timing and pulse width designated by the control circuit 60. The voltage amplitude of the data write pulse corresponds to the program voltage Vpgm produced by the high-voltage generating circuit 80.
With such a structure, the write condition storage region 14 formed from a part of the memory array 10 stores pre-adjusted data write conditions of every sector. In the normal operation, optimal data write conditions corresponding to the sector of interest are read upon every write operation, so that the data can be written based on the optimal data write conditions.
In FIG. 26, the write condition storage region 14 is formed from the memory cells arranged on the same memory array 10 as that of the memory cells of the normal region 12. Such a structure causes the following problems.
FIGS. 27A to 27C are conceptual diagrams illustrating the problems regarding the arrangement of the write condition storage region.
It is now assumed that the normal region 12 of the memory array 10 is formed from 16 k word lines, i.e., 16 k sectors, and has 2 k memory cell columns (bit lines).
In the structure of FIG. 27A, the write condition storage region 14 has independent sectors respectively corresponding to the sectors of the normal region 12. These sectors are arranged in the same manner as that of the sectors of the normal region 12. In this case, the data write conditions suitable for each sector of the normal region 12 can be stored in the respective sector of the write condition storage region 14.
In the structure of FIG. 27A, however, the write condition storage region 14 also includes in every sector a memory cell group for storing 2 k-bit data. On the other hand, the data write conditions suitable for each sector are generally set in the following manner: for example, a suitable setting level of the voltage amplitude and pulse width of the data write pulse or the like is selected from at most about several setting levels, based on the data write performance of the sector of interest.
The data for selecting such a setting level can be stored with a small number of bits. Therefore, providing the memory cells corresponding to 2 k bits is extremely wasteful. Referring to FIG. 27A, the data write conditions can be stored in a small region 14a of the write condition storage region 14. The remaining region 14b of the write condition storage region 14 is wasted in terms of the layout. This unnecessarily increases the area of the memory array 10.
In the structure of FIG. 27B, the write condition storage region 14 corresponds only to the region 14a of FIG. 27A. Accordingly, other circuitry can be provided using a region corresponding to the region 14b of FIG. 27A, thereby reducing the limitations on the layout.
However, the structure of FIG. 27B includes the memory cell columns corresponding to both the normal region 12 and the write condition storage region 14, and the memory cell columns corresponding only to the normal region 12, resulting in the difference in bit length between the memory cell columns. Therefore, the bit line load is different from memory cell column to memory cell column, making it difficult to stabilize the operation.
In the structure of FIG. 27C, the normal region 12 is extended in the column direction for the write condition storage region 14. Such a structure can suppress the area penalty.
In the structure of FIG. 27C, however, both the normal region 12 and the write condition storage region 14 are selected by a common word line. Therefore, upon erasing the data stored in the normal region 12, the data write conditions stored in the write condition storage region 14 may also be erased.
Therefore, the data write conditions stored in the write condition storage region 14 must be saved to a register or the like before erasing the data from the normal region 12, and written back to the write condition storage region 14 after completion of the erasing. This increases the time required for the data erase operation.
Accordingly, it is possible to form the write condition storage region 14 from the sectors independent of those of the normal region 12 as shown in FIG. 26 and to store the data write conditions corresponding to a plurality of sectors of the normal region 12 in a single sector of the write condition storage region 14.
FIG. 28 is a conceptual diagram showing the structure of the write condition storage region 14 of FIG. 26.
Referring to FIG. 28, the data write conditions of each sector of the normal region 12 are represented by 2-bit data. This enables the data write conditions to be set in 22=4 levels in the data write operation to each sector.
Accordingly, the data write conditions corresponding to 1 k sectors of the normal region 12 can be stored in a single sector of the write condition storage region 14. For example, the respective data write conditions corresponding to the first (#1) to 1024th (#1024) sectors of the normal region 12 can be stored in the first sector ES1 of the write condition storage region 14.
Thus, the write condition storage region 14 can store the respective data write conditions corresponding to 16 k sectors of the normal region 12 in the memory cells of 16 word lines by 2 k bit lines. As a result, the area of the write condition storage region 14 can be reduced without causing the problems described in connection with FIGS. 27A to 27C.
However, the structure of FIG. 28 is problematic in that the read disturb to the memory cells of the write condition storage region 14 occurs when the data is sequentially written to a plurality of successive sectors.
The read disturb results from an electric field applied between the control gate and the substrate in the data read operation. Moreover, a voltage, although being lower than the data write voltage, is applied between the gate and drain of the memory cell in the data read operation. This may possibly results in the soft write, a phenomenon that the data is erroneously written to the memory cell in the erase state.
For example, it is now assumed that the data is successively written to the first (#1) to 1024th (#1024) sectors of the normal region 12. In this case, the data is repeatedly read from the sector ES1 of the write condition storage region 14 every time the data is written to the sector of the normal region 12.
Every time the data is read from the sector ES1, each of the 2 k memory cells in the sector ES1 is subjected to the read disturb. Accordingly, the storage data in these memory cells may possibly be damaged.
Such a phenomenon may possibly cause erroneous selection of the data write conditions of the sectors upon writing the data to the normal region 12, thereby hindering a normal data write operation.
It is an object of the present invention to appropriately set the data write conditions or data erase conditions of each unit region that is subjected to a single write operation in a non-volatile semiconductor memory device like a flash memory.
It is another object of the present invention to appropriately set the write conditions for writing a respective level, in a multi-level storage non-volatile semiconductor memory device to which a plurality of data levels can be written.
In summary, a non-volatile semiconductor memory device according to the present invention includes a first memory array, an operation condition storage portion, an electric signal control portion, and a selecting portion. The first memory array stores data in a non-volatile manner. The first memory array is divided into a plurality of first unit regions each corresponding to a unit subjected to a single prescribed operation of writing or erasing data. The operation condition storage portion retains setting condition data of the prescribed operation to the first memory array. The operation condition storage portion includes a second memory array including a plurality of second unit regions each corresponding to a unit subjected to a single data read operation. Each of the second unit regions stores the setting condition data corresponding to one of the plurality of first unit regions in a non-volatile manner. The electric signal control portion determines, based on the setting condition data read from the operation condition storage portion, a setting condition of an electric signal for conducting the prescribed operation to a selected one of the plurality of first unit regions. The selecting portion supplies to the selected one of the first unit regions the electric signal according to the setting condition determined by the electric signal control portion.
Accordingly, a primary advantage of the present invention is that, even when the data is successively written to or erased from the first unit regions of the first memory array, the setting condition data corresponding to a selected first unit region can be read from the second memory array without repeatedly conducting a data read operation from the same second unit region. This enables the prescribed operation to be conducted on appropriate conditions on a sector-by-sector basis, and also prevents damages to the setting condition data stored in the second storage region. Moreover, since the second unit regions are arranged in the second memory array separately from the first unit regions, the size of the second memory array can be efficiently determined according to the content of the setting condition data.
According to another aspect of the present invention, a non-volatile semiconductor memory device includes a memory array, an electric signal control portion, and a selecting portion. The memory array includes a plurality of memory cells each being capable of storing a plurality of data levels in a non-volatile manner. The memory array is divided into a plurality of unit regions each corresponding to a unit subjected to a single data write operation. The electric signal control portion determines a setting condition of a plurality of electric signals for conducting a plurality of unit write operations corresponding to the plurality of data levels, respectively. The plurality of unit write operations form the single data write operation. The electric signal control portion sets the setting condition of each of the unit write operations except for an initial unit write operation thereof, according to a result of at least one of the unit write operations that have already been conducted in the same data write operation. The selecting portion supplies, in the plurality of unit write operations, the plurality of electric signals according to the setting condition determined by the electric signal control portion to a selected one of the plurality of unit regions.
Accordingly, in a single data write operation, the setting condition of the subsequent unit write operation except for the initial unit write operation can be appropriately determined based on the data write characteristics of the first unit region that are determined based on the result of the unit write operation that has already been conducted. As a result, the data write speed is increased as well as variation in characteristics after the data write operation can be suppressed in each of the first unit regions.
According to still another aspect of the present invention, a non-volatile semiconductor memory device includes a memory array, an electric signal control portion, and a selecting portion. The memory array includes a plurality of memory cells each being capable of storing a plurality of data levels in a non-volatile manner. The memory array is divided into a plurality of unit regions each corresponding to a unit subjected to a single data write operation. Each of the unit regions includes a management data region for storing a result of the data write operation conducted previously. The electric signal control portion determines a setting condition of a plurality of electric signals for conducting a plurality of unit write operations corresponding to said plurality of data levels, respectively, based on the result read from the management region. The plurality of unit write operations forms the single data write operation. The selecting portion supplies, in the plurality of unit write operations, the plurality of electric signals according to the setting condition determined by the electric signal control portion to a selected one of the plurality of unit regions.
Accordingly, the setting conditions of an initial one of the unit write operations can also be set optimally, with suppressing the variation in data write characteristics between the unit regions.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.